This invention relates generally to output buffer circuits as used in integrated circuits such as programmable logic devices, and more particularly the invention relates to an output buffer which has reduced noise when switching states of an output.
The output pins and associated capacitances of integrated circuits are often connected to external ground leads and external voltage leads through pull-down and pull-up transistors, respectively, which are controlled by data signals generated within the integrated circuit. The leads have inductance associated therewith, and a voltage given by the inductance, L, multiplied by the time rate of change of current, di/dt, develops across the leads during voltage transitions. When multiple outputs connected to the leads switch, the time rate of change of current, di/dt, can be high thereby causing noise voltages to be developed across the leads. Consequently, the internal ground reference network can be at a different potential than the external ground thereby resulting in device inputs and outputs behaving differently than expected with consequential erroneous circuit operation.
Many buffer circuits have been proposed for reducing noise on output terminals by limiting the rate at which the output pin capacitance can charge and discharge, thus reducing the time rate of change of current. U.S. Pat. No. 4,789,796 discloses an output buffer having a sequentially switched output; U.S. Pat. No. 4,771,195 utilizes a plurality of subtransistors in the charging/discharging paths; U.S. Pat. No. 4,638,187 includes a pull-up circuit having parallel P channel and N channel FETs and a pull-down circuit having a pair of N channel FETs with a delay resistance between their gates; and U.S. Pat. No. 4,961,010 utilizes primary and secondary pull-up and pull-down transistors with delay resistance to delay turn on of the primary transistors.